As the semiconductor memory has become larger in scale with micro-fabrication technology, a defective cell may exist in a core array with an increased possibility. A defect in the memory cell itself may cause such a defective cell, as well as a short circuit between neighboring bit lines may constitute one of other major causes. Such a defective cell is normally detected in the test process before the shipment, and the detected defective cell area is replaced by a redundant cell array for relieving the core array. The substitution method which has most popularly been applied hereto is to replace a block of a predetermined size in the core array by a redundant cell array of the same predetermined size. According to this conventional method, a core array is divided into a plurality of predetermined blocks in a fixed manner. A block address for a block having the detected defective cell is stored in a defective cell information storage area, and thus the redundant cell array is substituted. When there is an access from the outside, the redundant cell array is selected in place of the block corresponding to the address stored in this defective cell information storage area.
FIG. 1 shows a diagram illustrating the conventional redundant configuration of a flash memory, an example of the semiconductor memory. In this memory, there is provided a redundant cell array RA, which is located neighboring to a core array COA. The core array COA is constituted of, as an example, sixteen (16) I/O blocks I/O0-15, and a reference cell array RefA disposed in a neighboring position. An address A (23:0) supplied at the time of access is input to an address buffer ADD-Buf, and divided into a row address A (23:7) and a column address A (6:0) which are further supplied to an X decoder XDEC and a Y decoder YDEC respectively. The column address A (6:0) is also supplied to a Y decoder YDECR of the redundant cell array RA. In the above-mentioned memory, each I/O block includes a plurality of bit lines BL, 64 memory cells MC disposed between the neighboring bit lines, and a plurality of word lines WL. Each I/O block can store 128-bit data for one word line WL.
In the example shown in FIG. 1, the redundant cell array RA is of the same size as each I/O block in the core array. The I/O block I/O12 which includes a defective cell is replaced by the redundant cell array RA. Here, the redundant cell array RA is not necessarily of the same size as each I/O block. When the RA is smaller in size than the I/O block, a portion of the I/O block area is replaced by the redundant cell array RA.
The flash memory shown in FIG. 1 is a nonvolatile memory in which each memory cell has a trap gate. Depending on whether or not charge is stored in both sides of the trap gate, the transistor threshold voltage of the memory cell becomes different. Stored data are read out making use of this difference. For example, when the bit located on the left side of a memory cell MC0 is to be read out, a word line WL is set to a predetermined voltage, and a bit line BL0 is grounded. Whether or not a cell current is generated in the memory cell is detected through a bit line BL1. At this time, in order to eliminate an influence of the memory cell MC1 connected on the same bit line BL1 but positioned on the opposite side, a bit line BL2 is driven to a pre-charge level. On the other hand, when the bit located on the right side of the memory cell MC0 is to be read out, the control is carried out based on the bit line relation with left and right reversed. These kind of memory cell array structure is called a virtual bit line structure, in which one of the bit line functions as a read bit line.
The memory cell shown in FIG. 1 is in distribution in the market as a commercial product. However, the inventors of the present invention have no knowledge of either patent document or non-patent document concretely disclosing arts of the aforementioned memory cell. The following patent document disclosed is known as a redundant configuration of a synchronous dynamic random access memory (DRAM).
[Patent Document]
An official gazette of the Japanese unexamined patent, publication number Hei-8-102186. (Date of publication: 16th of Apr., 1996)
One feature of the virtual bit line configuration is that a predetermined defective cell area centering the defective cell is replaced by the redundant cell array. For example, in FIG. 1, when there is a defect in the memory cell MC0 located in the boundary area of an I/O block, or when there is a short circuit between the bit lines BL0 and BL1, it is not possible to relieve from the defect if only the I/O block concerned is simply replaced by the redundant cell array RA. The reason is, because one bit line depends on the state of a memory cell pair connected to the bit line concerned, it is necessary to eliminate the influence of the memory cell operation connected to the bit line by properly controlling the potential of the non-illustrated neighboring bit line to the left side of the bit line BL0 when reading the cell current of the memory cell MC0 via the bit line BL0. Therefore, it is necessary to arrange the substitution object area of the core array so that the defective cell does not exist at the boundary of the substitution object area.
To cope with this problem, there has been proposed to set the substitution object area by means of a “moving window” scheme. According to this scheme, an area centering the detected defective cell is set as a substitution object area each time, instead of fixedly determining in advance the substitution object area of the core array. In other words, the substitution object area is moved depending on defective cell locations. More specifically, the address of an area centering the detected defective cell is recorded in the defective cell information storage area, and the redundant cell array is selected to substitute for the recorded address area.
According to such a moving window scheme, when a defective cell is detected in the test process, information of the predetermined area which centers the defective cell, for example the top address of the area concerned, is written into the defective cell information storage area. Accordingly, in case the defective cell is located on the boundary of a memory block, the both sides of the memory block boundary in the core array is set as the substitution object area. In this case, depending on the access address, it is necessary to check which of the memory block output located on either side of the boundary is to be replaced by the redundant cell array output. In addition, as another problem to be solved, when the defective cell is located in the edge portion of the core array, the both sides of the boundary edge portion of the core array are to be set as the substitution object area. However, in this case, because there is no memory block outside the boundary of the edge portion of the core array, it is not possible to use the same substitution check function as is applicable for the case of the defective cell being located on the boundary of the memory block of the core array.
Such a problem related to the edge boundary of the cell array also arises when the reference array is provided in the neighboring location to the core array. In the reference array, there is disposed a reference cell which is selected simultaneously when the memory cell in the core array is selected at the time of readout or verification. Accordingly, the same problem as the above arises when the defective cell is located near the boundary of the core array and the reference array, because the substitution object area includes the reference array outside the core array in this case.